Staff DV Engineer
@ E-SpaceStaff DV Engineer
This job is still taking applications, but it's been up a while.
About the job
E-Space is developing innovative space-based communication systems for IoT, focusing on satellite and terrestrial connectivity, with a mission to expand global connectivity and protect space.
Requirements
- Verilog and SystemVerilog proficiency
- UVM verification experience
- C/C++ coding skills
- Scripting in Perl or Python
- Verification test writing
Qualifications
- 6+ years verification experience
- Passion for satellite technology
- Experience leading verification efforts
- Deep knowledge of UVM methodology
- Interest in space industry
Full job description
Requirements
HDL & Verification Methodology
· Strong proficiency in Verilog and SystemVerilog
· Experience writing tests within an existing UVM verification environment
· Solid understanding of UVM architecture and methodology
Programming & Scripting
· Ability to write C/C++ code for verification purposes
· Some scripting experience in Perl or Python
Verification Planning & Execution
· Ability to contribute to and help write test plans
· Experience writing and maintaining verification tests
· Ability to debug RTL simulations independently
Leadership
· Experience leading design verification efforts at the block level
· Experience driving code coverage closure on assigned blocks
What you bring to this role:
6+ years of design verification experience in the semiconductor industry
Additional Requirements
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