Design Engineer
@ cadenceDesign Engineer
About the job
Cadence hires leaders and innovators to make a tech impact. The role involves designing, testing, and optimizing electronic systems for EDA and semiconductor IP, with collaborative R&D and customer delivery focus.
Requirements
- Master’s in Electrical or related field
- Knowledge of VLSI design
- ASIC digital design flow
- Timing analysis and optimization
- Scripting in TCL, Perl
Qualifications
- Digital IC implementation experience
- Experience in RTL to GDSII flow
- Understanding processor architectures
- Strong problem-solving skills
Full job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Duties:
- Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
- Utilize graduate-level research and analysis skills to understand complex customer challenges in Integrated Circuit (IC) design implementation on latest technology nodes.
- Identify solutions by using Cadence products in digital implementation and signoff space.
- Create specifications for the solutions and work with multiple Research and Development (R&D) teams for their implementation.
- Validate and deliver solutions at customer’s end.
- Debug issues faced with Cadence timing signoff and optimization technology on complex customer designs.
- Develop scripts to increase the efficiency and reliability of solutions.
- Some telecommuting permitted.
Qualifications:
- Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Utilize Very Large-Scale Integration (VLSI) to design and optimize complex integrated circuits on a single chip
- Application Specific Integrated Circuit (ASIC) digital design flow and methodology
- Utilize Static Timing Analysis (STA) to verify and optimize timing critical paths
- Complete digital implementation flow from RTL to GDSII, including logic synthesis, physical design, and timing closure
- Computer Architecture, specifically processor pipelines, clock domains, memory hierarchy, power distribution, and on-chip interconnects
- Shell scripting, TCL and Perl in EDA tools
The annual salary range for California is $115,253 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the base salary range is a guideline, and individual total compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.